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| SSM4575M COMPLEMENTARY N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement Low on-resistance Fast switching performance D2 D1 D1 D2 N-Ch BV DSS 60V 36m 6A -60V 72m -4.2A R DS(ON) G2 S2 ID SO-8 S1 G1 Description Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and costeffectiveness. The SO-8 package is widely preferred for commercial and industrial surface mount applications and is well suited for low-voltage applications such as DC/DC converters. P-Ch BV DSS RDS(ON) ID D1 D2 G1 S1 G2 S2 Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Continuous Drain Current3 Current3 1 Rating N-channel 60 20 6 4.7 30 2.0 0.016 -55 to 150 -55 to 150 P-channel -60 20 -4.2 -3.3 -30 Units V V A A A W W/C C C Pulsed Drain Current Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit C/W Rev.1.01 7/05/2004 www.SiliconStandard.com 1 of 7 SSM4575M N-channel Electrical Characteristics @ T j=25oC(unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 60 1 Typ. 0.04 8 18 5 10 10 6 32 10 160 117 Max. Units 36 42 3 1 25 100 29 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BVDSS/ Tj RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Breakdown Voltage Temperature Coefficient Reference to 25C,ID=1mA Static Drain-Source On-Resistance 2 VGS=10V, ID=5A VGS=4.5V, ID=3A VDS=VGS, ID=250uA VDS=10V, ID=5A Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=60V, VGS=0V VDS=48V, VGS=0V VGS=20V ID=5A VDS=48V VGS=4.5V VDS=30V ID=1A RG=3.3 ,VGS=10V RD=30 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1670 2670 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 2 Test Conditions IS=1.7A, VGS=0V IS=5A, VGS=0V dI/dt=100A/s Min. - Typ. 34 48 Max. Units 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge Rev.1.01 7/05/2004 www.SiliconStandard.com 2 of 7 SSM4575M P-channel Electrical Characteristics @ T j=25oC(unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=70 C) o o Test Conditions VGS=0V, ID=-250uA 2 Min. -60 -1 - Typ. -0.04 6 21 5 9 12 6 82 36 157 130 Max. Units 72 88 -3 -1 -25 100 34 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BVDSS/Tj RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Breakdown Voltage Temperature Coefficient Reference to 25C,ID=-1mA VGS=-10V, ID=-4A VGS=-4.5V, ID=-3A VDS=VGS, ID=-250uA VDS=-10V, ID=-4A VDS=-60V, VGS=0V VDS=-48V, VGS=0V VGS=20V ID=-4A VDS=-48V VGS=-4.5V VDS=-30V ID=-1A RG=3.3 ,VGS=-10V RD=30 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1780 2850 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage2 Reverse Recovery Time 2 Test Conditions IS=-1.7A, VGS=0V IS=-4A, VGS=0V dI/dt=-100A/s Min. - Typ. 43 87 Max. Units -1.2 V ns nC Reverse Recovery Charge Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135C/W when mounted on min. copper pad. Rev.1.01 7/05/2004 www.SiliconStandard.com 3 of 7 SSM4575M N-channel 60 50 T A = 25 o C 50 ID , Drain Current (A) 40 ID , Drain Current (A) 10V 7.0V 5.0V 4.5V TA=150oC 40 10V 7.0V 5.0V 4.5V 30 30 20 20 V G =3.0V 10 V G =3.0V 10 0 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 7 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 38 1.8 36 ID=3A Normalized RDS(ON) T A =25 C o 1.6 I D =5A V G =10V 1.4 34 RDS(ON) (m ) 1.2 32 1.0 30 0.8 28 0.6 2 4 6 8 10 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 1.5 5 1.3 4 Normalized VGS(th) (V) 1.1 3 IS(A) 0.9 T j =150 o C 2 T j =25 o C 0.7 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 0.3 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Rev.1.01 7/05/2004 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 4 of 7 SSM4575M N-channel f=1.0MHz 14 10000 VGS , Gate to Source Voltage (V) 12 I D =5A V DS =48V C iss 10 8 C (pF) 1000 6 4 2 C oss C rss 0 0 5 10 15 20 25 30 35 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (Rthja) Duty factor=0.5 0.2 10 0.1 0.1 0.05 ID (A) 1ms 1 0.02 10ms 100ms 0.1 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja =135o C/W T A =25 o C Single Pulse 1s DC 0.01 0.1 1 10 100 1000 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off)tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform Rev.1.01 7/05/2004 www.SiliconStandard.com 5 of 7 SSM4575M P-channel 40 40 35 T A = 25 C o -ID , Drain Current (A) -ID , Drain Current (A) 30 -10V -7.0V -5.0V -4.5V 35 TA=150oC 30 25 25 -10V -7.0V -5.0V -4.5V 20 20 15 15 V G =-3.0V 10 V G =-3.0V 10 5 5 0 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 7 8 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 80 1.8 ID=-3A 75 1.6 ID=-4A V G =-10V T A =25C Normalized R DS(ON) 1.4 RDS(ON) (m ) 70 1.2 1.0 65 0.8 60 0.6 2 4 6 8 10 -50 0 50 100 150 -V GS ,Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 1.6 4 1.3 Normalized -VGS(th) (V) 3 -IS(A) 1.1 2 T j =150 o C T j =25 o C 0.8 1 0.6 0 0.3 0 0.2 0.4 0.6 0.8 1 1.2 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C) o Fig 5. Forward Characteristic of Reverse Diode Rev.1.01 7/05/2004 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 6 of 7 SSM4575M P-channel 16 f=1.0MHz 10000 -VGS , Gate to Source Voltage (V) I D =-4A V DS =-48V 12 8 C (pF) C iss 1000 4 C oss C rss 0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics 100 Fig 8. Typical Capacitance Characteristics 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 0.2 10 0.1 0.1 1ms -ID (A) 1 0.05 10ms 100ms 0.02 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135oC/W 0.1 T A =25 C Single Pulse o 1s DC 0.01 0.1 1 10 100 1000 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area VDS 90% Fig 10. Effective Transient Thermal Impedance VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.1.01 7/05/2004 www.SiliconStandard.com 7 of 7 |
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